VLSl Architectures for Computing Multiplications
نویسنده
چکیده
Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and ik some cnptoqaphic algorithms. There is a need for good multiplication and inversion clgorithms thct can be easily realized on VISI chips. Massey and Omura recent& developed a new multiplication algorithm for Galois fie;ds based on a normal basis representation In this paper, a pipeline structure is developed to realize t!:e hlassey-Omura multiplier in the finite field CF(19" ). With the simple squaring property of the normal-basis representation used togerher with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(Zm). The desipis developed .for the Masse).-Omura multiplier and the computation of inzerse elements are reguk, simple, expandable and, therefore, natural& suitable for VLSI implementation
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